6-9 file number 3590.5 note: the design of the SP721 scr/diode esd protection arrays is covered by littelfuse patent 4567500. 1-800-999-9445 or 1-847-824-1188 | copyright littelfuse, inc. 1998 SP721 electronic protection array for esd and over-voltage protection the SP721 is an array of scr/diode bipolar structures for esd and over-voltage protection to sensitive input circuits. the SP721 has 2 protection scr/diode device structures per input. there are a total of 6 available inputs that can be used to protect up to 6 external signal or bus lines. over- voltage protection is from the in (pins 1 - 3 and pins 5 - 7) to v+ or v-. the scr structures are designed for fast triggering at a threshold of one +v be diode threshold above v+ (pin 8) or a -v be diode threshold below v- (pin 4). from an in input, a clamp to v+ is activated if a transient pulse causes the input to be increased to a voltage level greater than one v be above v+. a similar clamp to v- is activated if a negative pulse, one v be less than v-, is applied to an in input. standard esd human body model (hbm) capability is: refer to figure 1 and table 1 for further detail. refer to application notes an9304 and an9612 for additional information. pinout SP721 (pdip, soic) top view features esd interface capability for hbm standards - mil std 3015.7 . . . . . . . . . . . . . . . . . . . . . . . . . . 15kv - iec 1000-4-2, direct discharge, single input. . . . . . . . . . . . . . . . . . . . . . . . 4kv (level 2) two inputs in parallel . . . . . . . . . . . . . . . . 8kv (level 4) - iec 1000-4-2, air discharge. . . . . . . . . . 15kv (level 4) high peak current capability - iec 1000-4-5 (8/20 s) . . . . . . . . . . . . . . . . . . . . . . 3a - single pulse, 100 s pulse width . . . . . . . . . . . . . . 2a - single pulse, 4 s pulse width . . . . . . . . . . . . . . . . 5a designed to provide over-voltage protection - single-ended voltage range to . . . . . . . . . . . . . . .+30v - differential voltage range to . . . . . . . . . . . . . . . . 15v fast switching . . . . . . . . . . . . . . . . . . . . . . 2ns rise time low input leakages . . . . . . . . . . . . . . 1na at 25 o c typical low input capacitance. . . . . . . . . . . . . . . . . . . 3pf typical an array of 6 scr/diode pairs operating temperature range . . . . . . . . . -40 o c to 105 o c applications microprocessor/logic input protection data bus protection analog device input protection voltage clamp functional block diagram hbm standard mode r c esd (v) iec 1000-4-2 air 330 ? 150pf >15kv direct 330 ? 150pf >4kv direct, dual pins 330 ? 150pf >8kv mil-std-3015.7 direct, in-circuit 1.5k ? 100pf >15kv ordering information part no. temp. range ( o c ) package pkg. no. SP721ap -40 to 105 8 ld pdip e8.3 SP721ab -40 to 105 8 ld soic m8.15 SP721abt -40 to 105 8 ld soic tape and reel m8.15 in in in v- 1 2 3 4 8 7 6 5 v+ in in in 4 v+ v- in 3, 5-7 in in 1 8 2 data sheet january 1998 [ /title (SP721 ) /sub- ject (elec- tronic protec- tion array for esd and over- volt- age protec- tion) /autho r () /key- words (tvs, tran- sient sup- pres- sion, protec- tion, esd, iec, emc, elec- tro- magnet ic com-
6-10 esd capability esd capability is dependent on the application and de?ed test standard. the evaluation results for various test standards and methods based on figure 1 are shown in table 1. for the ?odified?mil-std-3015.7 condition that is defined as an ?n-circuit?method of esd testing, the v+ and v- pins have a return path to ground and the SP721 esd capability is typically greater than 15kv from 100pf through 1.5k ? . by strict definition of mil-std-3015.7 using ?in-to-pin?device testing, the esd voltage capability is greater than 6kv. the mil-std-3015.7 results were determined from at&t esd test lab measurements. the hbm capability to the iec 1000-4-2 standard is greater than 15kv for air discharge (level 4) and greater than 4kv for direct discharge (level 2). dual pin capability (2 adjacent pins in parallel) is well in excess of 8kv (level 4). for esd testing of the SP721 to eiaj ic121 machine model (mm) standard, the results are typically better than 1kv from 200pf with no series resistance. absolute maximum ratings thermal information continuous supply voltage, (v+) - (v-) . . . . . . . . . . . . . . . . . . +35v forward peak current, i in to v cc , i in to gnd (refer to figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2a, 100 s esd ratings and capability (figure 1, table 1) load dump and reverse battery (note 2) thermal resistance (typical, note 1) ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 maximum storage temperature range . . . . . . . . . . -65 o c to 150 o c maximum junction temperature (plastic package) . . . . . . . . .150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c (soic lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?ations t a = -40 o c to 105 o c, v in = 0.5v cc , unless otherwise speci?d parameter symbol test conditions min typ max units operating voltage range, v supply = [(v+) - (v-)] v supply - 2 to 30 - v forward voltage drop in to v- in to v+ v fwdl v fwdh i in = 1a (peak pulse) - - 2 2 - - v v input leakage current i in -20 5 +20 na quiescent supply current i quiescent - 50 200 na equivalent scr on threshold note 3 - 1.1 - v equivalent scr on resistance v fwd /i fwd ; note 3 - 1 - ? input capacitance c in -3-pf input switching speed t on -2-ns notes: 2. in automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse b attery. when the v+ and v- pins are connected to the same supply voltage source as the device or control line under protection, a current limiti ng resistor should be connected in series between the external supply and the SP721 supply pins to limit reverse battery current to within the rat ed maximum limits. bypass capacitors of typically 0.01 f or larger from the v+ and v- pins to ground are recommended. 3. refer to the figure 3 graph for definitions of equivalent ?cr on threshold?and ?cr on resistance? these characteristics a re given here for thumb-rule information to determine peak current and dissipation under eos conditions. table 1. esd test conditions standard type/mode r d c d v d mil-std-3015.7 modified hbm 1.5k ? 100pf 15kv standard hbm 1.5k ? 100pf 6kv iec 1000-4-2 hbm, air discharge 330 ? 150pf 15kv hbm, direct discharge 330 ? 150pf 4kv hbm, direct discharge, two parallel input pins 330 ? 150pf 8kv eiaj ic121 machine model 0k ? 200pf 1kv h.v. supply v d in dut c d r 1 iec 1000-4-2: r 1 50 to 100m ? r d charge switch discharge switch mil-std-3015.7: r 1 1 to 10m ? figure 1. electrostatic discharge test SP721
6-11 figure 2. low current scr forward voltage drop curve figure 3. high current scr forward voltage drop curve figure 4. typical application of the SP721 as an input clamp for over-voltage, greater than 1v be above v+ or less than -1v be below v- 600 800 1000 1200 forward scr voltage drop (mv) 100 80 60 40 20 0 forward scr current (ma) t a = 25 o c single pulse 2.5 2 1.5 1 0.5 0 forward scr current (a) t a = 25 o c single pulse v fwd i fwd 01 23 forward scr voltage drop (v) equiv. sat. on threshold ~ 1.1v +v cc input drivers SP721 input protection circuit (1 of 6 shown) or signal sources in 5 - 7 in 1 - 3 SP721 v- to +v cc linear or digital ic interface v+ +v cc SP721
6-12 peak transient current capability of the SP721 the peak transient current capability rises sharply as the width of the current pulse narrows. destructive testing was done to fully evaluate the SP721 s ability to withstand a wide range of peak current pulses vs time. the circuit used to generate current pulses is shown in figure 5. the test circuit of figure 5 is shown with a positive pulse input. for a negative pulse input, the (-) current pulse input goes to an SP721 ?n input pin and the (+) current pulse input goes to the SP721 v- pin. the v+ to v- supply of the SP721 must be allowed to ?at. (i.e., it is not tied to the ground reference of the current pulse generator.) figure 6 shows the point of overstress as de?ed by increased leakage in excess of the data sheet published limits. the maximum peak input current capability is dependent on the ambient temperature, improving as the temperature is reduced. peak current curves are shown for ambient temperatures of 25 o c and 105 o c and a 15v power supply condition. the safe operating range of the transient peak current should be limited to no more than 75% of the measured overstress level for any given pulse width as shown in the curves of figure 6. note that adjacent input pins of the SP721 may be paralleled to improve current (and esd) capability. the sustained peak current capability is increased to nearly twice that of a single pin. + - voltage probe + - r 1 ~ 10 ? typical v x v x adj. 10v/a typical r 1 (-) (+) c1 ~ 100 f c1 variable time duration current pulse generator 1 2 3 4 8 7 6 5 v+ in in in in in in v- SP721 current sense figure 5. typical SP721 peak current test circuit with a variable pulse width input 0.001 0.01 0.1 1 pulse width time (ms) peak current (a) 10 7 6 5 4 3 2 1 0 t a = 105 o c 100 1000 caution: safe operating conditions limit of the values shown on each curve. pulse width to be no greater than 75% the maximum peak current for a given v+ to v- supply = 15v t a = 25 o c figure 6. SP721 typical single pulse peak current curves showing the measured point of overstress in amperes vs pulse width time in milliseconds SP721
6-13 SP721 dual-in-line plastic packages (pdip) c l e e a c e b e c -b- e1 index 1 2 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a 1 -a- 0.010 (0.25) c a m bs notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?o series symbol list?in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protru- sions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be per- pendicular to datum . 7. e b and e c are measured at the lead tips with the leads uncon- strained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e8.3 (jedec ms-001-ba issue d) 8 lead dual-in-line plastic package symbol inches millimeters notes min max min max a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.355 0.400 9.01 10.16 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n8 89 rev. 0 12/93
6-14 SP721 small outline plastic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?o series symbol list?in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ??does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ??does not include interlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ??is the length of terminal for soldering to a substrate. 7. ??is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?? as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 o 8 o 0 o 8 o - rev. 0 12/93
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